1. Field of the Invention
The invention relates to a method of reducing power leakage in processors or ICs, and in particular to a method of power-gating instruction scheduling for power leakage reduction.
2. Description of the Related Art
Overall power dissipation in semiconductor application comprises static power dissipation and dynamic power dissipation, generated by current leakage and switching transient current in complementary metal oxides semiconductor (CMOS) circuits, respectively. As semiconductor technology continues to scale down to deep-submicron levels, power leakage gains more significance in the total power dissipation.
In recent years, many power-gating mechanisms have been developed and employed to reduce the static power loss generated by the current leakage in CMOS circuits. The power-gating mechanisms insert power-gating instructions into a program to reduce power leakage of power-gated components in the processor. The power-gating instructions comprise power-off and power-on instructions to shut down inactive power-gated components.
ROC. Pat. Pub. No. 00519599 discloses architecture and complier solutions to employ a power-gating mechanism to reduce the current leakage in power-gated components of a processor executing a program. The power-gating mechanism analyzes utilization of the power-gated components by data-flow analysis on the basis of the program and then inserts power-off and power-on instructions into the program to shut down the inactive power-gated components.
However, the power-off and power-on instructions increase execution time of the program and increase code size. With the development of semiconductor manufacturing technologies, the increasing number of power-gated components in a processor aggravates the above drawbacks. Moreover, fetching and decoding of power-gating instructions, and shut-down and wake-up procedures all results in power loss. Power loss from wake-up is derived from peak-voltage requirements. Therefore, it is advantageous necessary to reduce power-gating instructions.